1. Field of the Invention:
This invention relates to semiconductor packaging technology, and more particularly, to a semiconductor package with enhanced chip groundability and method of fabricating the same.
2. Description of Related Art:
Wire-bonding (WB) technology is a widely-used electrical connecting method in chip-packaging processes, which is used to electrically connect an array of pads on the chip, including ground pads, power pads, and signal I/O pads by means of bonding wires to corresponding connecting points on a substrate, so as to allow the internal circuitry of the packaged chip to be electrically connected to external printed circuit board.
One drawback to the conventional electrical connection between a chip and a substrate via bonding wires, however, is that wire routablity would be a problem, particularly in the case of the chip having a great number of densely-arranged ground/power and I/O pads to be electrically connected to the substrate. Moreover, as the chip is increased in the number of pads, it would require an increased number of bond wires, which are typically made of gold would result in high fabrication cost.
Moreover, by conventional methods, the wire-bonding process would make the total grounding path somewhat lengthy. Since this grounding path is considerably lengthy, it would result in the so-called ground-bouncing effect that would degrade the electrical performance of the package.
Related prior arts include, for example, U.S. Pat. No. 6,316,287, and U.S. Pat. No. 5,581,122, to name just a few.
U.S. Pat. No. 6,316,287 “CHIP SCALE SURFACE MOUNT PACKAGES FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME”, which discloses a packaging method that is characterized by extending the ground pads on the packaged chip and expose the back sides thereof and then forming a metallization layer to electrically connect the exposed back sides to the grounding plane on the substrate. One drawback to this invention, however, is that it would require complex procedural steps to implement.
U.S. Pat. No. 5,581,122 “PACKAGING ASSEMBLY WITH CONSOLIDATED COMMON VOLTAGE CONNECTIONS FOR INTEGRATED CIRCUITS”, which discloses a packaging method that is characterized by the use of a ground ring and a power ring to facilitate the electrically connecting of the chip's ground pads and power pads to the substrate. One drawback to this invention, however, is that the crossed arrangement of the ground ring and the power ring would make the fabrication process more complex and thus difficult to implement. Moreover, this patent nonetheless requires the use of ground wires for ground connection so that the grounding path is still considerably lengthy that would result in the above-mentioned ground-bouncing effect and thus degrade the electrical performance of the package.